An active matrix substrate used in liquid crystal display devices and the like has a switching element such as a thin-film transistor (hereinafter, “TFT”) in each pixel. Conventionally, a TFT having an amorphous silicon layer or a polycrystalline silicon layer as an active layer has been widely used as such a switching element.
There have been recent attempts to achieve a higher performing TFT while suppressing the number of manufacturing steps and cost by using an oxide semiconductor such as zinc oxide as a material for a TFT active layer (Patent Document 1 and Patent Document 2, for example). A TFT that uses an oxide semiconductor is referred to as an “oxide semiconductor TFT.” Oxide semiconductors have a higher mobility than amorphous silicon. Therefore, the oxide semiconductor TFT can operate at a faster speed than the amorphous silicon TFT. Furthermore, the oxide semiconductor film is formed with a process that is simpler than for the polycrystalline silicon film, and thus, the oxide semiconductor film can be applied to devices requiring a large area.
However, with an oxide semiconductor film, there is a risk that oxygen defects will create electron carriers in the TFT manufacturing process, such as in a heat treatment step and the like, causing a reduced resistance. Furthermore, in bottom-gate TFTs, the oxide semiconductor film at the bottom thereof is susceptible to damage during the step of etching the source and drain electrodes and the step of forming the interlayer insulating film. Thus, there have been problems such as the hysteresis of the TFT characteristics increasing, and stable TFT characteristics being difficult to achieve when using an oxide semiconductor film as an active layer of the TFT.
As a countermeasure, in Patent Document 1, for example, forming an insulating film (channel protective film) that functions as an etching stopper on the channel region of an active layer made of an oxide semiconductor has been proposed.
FIG. 14(a) is a plan view for describing a conventional oxide semiconductor TFT that has a channel protective film. FIG. 14 (b) is a cross-sectional view of FIG. 14(a) along the line A-A′.
The oxide semiconductor TFT includes: a substrate 1, a gate 3 provided on the substrate 1, a gate insulating layer 5 covering the gate 3, an oxide semiconductor layer 7 formed on the gate insulating layer 5, a channel protective layer (hereinafter, simply “protective layer”) 9 formed on the oxide semiconductor layer 7, and a source electrode 11 and a drain electrode 13 that are provided on the oxide semiconductor layer 7. The source electrode 11 and the drain electrode 13 are respectively electrically connected to the oxide semiconductor layer 7. Patent Document 1 discloses the usage of an amorphous oxide insulator as a protective layer 9.
In the process of manufacturing an oxide semiconductor TFT in Patent Document 1, when patterning is performed for the source electrode 11 and the drain electrode 13, the channel region of the oxide semiconductor layer 7 is protected by the protective layer 9. Thus, damage to the channel region of the oxide semiconductor layer 7 can be suppressed.
Furthermore, a process to continuously form an oxide semiconductor layer and a protective layer without exposing them to air is disclosed in Patent Document 2. For example, in FIG. 5 of Patent Document 2, a method of etching an oxide semiconductor layer and protective layer using the same mask has been proposed. A TFT with the same configuration as FIG. 5 of Patent Document 2 is shown in FIG. 15. In FIG. 15, the same reference characters as FIG. 14 are used for the same constituting elements.